Logic Gate Simulator Calculator
Free Logic gate simulator Calculator for logic & computer science. Enter values to get step-by-step solutions with formulas and graphs.
Formula
AND: A*B | OR: A+B | NAND: (A*B)' | NOR: (A+B)' | XOR: A^B | NOT: A'
Each logic gate implements a specific Boolean operation. AND outputs 1 when all inputs are 1. OR outputs 1 when any input is 1. NAND and NOR are the complements of AND and OR. XOR outputs 1 for an odd number of 1-inputs. NOT inverts a single input.
Worked Examples
Example 1: 2-Input NAND Gate Truth Table
Problem: Determine all possible outputs for a 2-input NAND gate with inputs A and B.
Solution: NAND = NOT(AND), so output is 0 only when both inputs are 1:\nA=0, B=0: NOT(0 AND 0) = NOT(0) = 1\nA=0, B=1: NOT(0 AND 1) = NOT(0) = 1\nA=1, B=0: NOT(1 AND 0) = NOT(0) = 1\nA=1, B=1: NOT(1 AND 1) = NOT(1) = 0
Result: NAND(A,B) outputs: 1, 1, 1, 0 | Only 0 when both inputs are 1
Example 2: 3-Input XOR for Parity Check
Problem: Use a 3-input XOR gate to determine the parity of the binary value 101.
Solution: XOR outputs 1 when an odd number of inputs are 1:\nInputs: A=1, B=0, C=1\nStep 1: A XOR B = 1 XOR 0 = 1\nStep 2: (A XOR B) XOR C = 1 XOR 1 = 0\nSince output is 0, there is an even number of 1s (two 1s).\nEven parity bit = 0.
Result: XOR(1,0,1) = 0 | Even parity confirmed (two 1-bits in input)
Frequently Asked Questions
What are the basic logic gates used in digital electronics?
The seven fundamental logic gates are AND, OR, NOT, NAND, NOR, XOR, and XNOR. The AND gate outputs 1 only when all inputs are 1, while the OR gate outputs 1 when any input is 1. The NOT gate (inverter) flips a single input, outputting 0 for 1 and vice versa. NAND and NOR are the inverted versions of AND and OR respectively, and are called universal gates because any other gate can be built using only NAND or only NOR gates. XOR (exclusive OR) outputs 1 when an odd number of inputs are 1, and XNOR outputs 1 when an even number of inputs are 1. These gates form the building blocks of all digital circuits, from simple combinational logic to complex processors containing billions of transistors.
How do logic gates work at the transistor level?
Logic gates are implemented using transistors, specifically MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) in modern CMOS technology. A CMOS gate uses complementary pairs of NMOS (pulls output to ground for logic 0) and PMOS (pulls output to VDD for logic 1) transistors. A CMOS inverter (NOT gate) uses just 2 transistors: one NMOS and one PMOS. When the input is high, NMOS conducts pulling the output low; when the input is low, PMOS conducts pulling the output high. A 2-input NAND gate uses 4 transistors: 2 NMOS in series (both must be on to pull output low) and 2 PMOS in parallel (either can pull output high). CMOS logic consumes power primarily during switching transitions, which is why it dominates modern digital design and enables billions of transistors on a single chip.
What is the difference between combinational and sequential logic?
Combinational logic circuits produce outputs that depend solely on the current input values, with no memory of previous states. Examples include adders, multiplexers, encoders, and the basic gate combinations this simulator models. Sequential logic circuits, in contrast, have memory elements (flip-flops or latches) that store state, making outputs dependent on both current inputs and the circuit history. Examples include counters, registers, and finite state machines. A flip-flop itself is built from cross-coupled NAND or NOR gates, creating a feedback loop that maintains a stable state. Most real digital systems combine both types: combinational logic computes the next state based on inputs and current state, while sequential elements store that state. Modern processors use billions of gates combining both types to implement instruction execution pipelines.
How is XOR gate used in arithmetic and error detection circuits?
The XOR gate is uniquely important in digital arithmetic and error detection because it naturally implements binary addition without carry (modulo-2 addition). A half adder, the simplest adding circuit, uses one XOR gate for the sum bit and one AND gate for the carry bit. Full adders chain these together to add multi-bit numbers. XOR is also fundamental in parity generators and checkers: XORing all bits of a data word produces a parity bit that can detect single-bit errors during transmission or storage. In CRC (Cyclic Redundancy Check) calculations used in networking and storage, XOR operations implement polynomial division over GF(2). Additionally, XOR is used in stream cipher encryption, toggle flip-flops, Gray-to-binary code conversion, and comparison circuits that check if two bits are equal. The self-inverse property of XOR (A XOR A = 0) makes it invaluable for these applications.
What is propagation delay and why does it matter in logic circuits?
Propagation delay is the time it takes for an input change to produce a corresponding output change in a logic gate, typically measured in nanoseconds or picoseconds. It matters because it limits the maximum operating frequency of a digital circuit. If a signal must pass through N gates in series (called the critical path), the total delay is roughly N times the individual gate delay, and the clock frequency cannot exceed 1/total_delay. In modern 5nm CMOS technology, a single gate delay is approximately 10-20 picoseconds, enabling clock frequencies above 4 GHz. Different gate types have different delays: inverters are fastest (fewest transistors), followed by NAND/NOR, then AND/OR, with XOR being slowest due to more transistors. Propagation delay also causes glitches (momentary incorrect outputs) when signals arrive at different times at a gates inputs, which is why careful timing analysis is essential in high-speed digital design.
What is De Morgans theorem and how does it apply to logic gates?
De Morgans theorem states two fundamental equivalences: NOT(A AND B) = NOT(A) OR NOT(B), and NOT(A OR B) = NOT(A) AND NOT(B). In gate terms, a NAND gate is equivalent to an OR gate with inverted inputs, and a NOR gate is equivalent to an AND gate with inverted inputs. This theorem is essential for circuit optimization because it allows designers to convert between AND-OR and NAND-NOR implementations freely. When drawing circuit diagrams, De Morgans theorem is represented by moving the inversion bubble from the output to the inputs (or vice versa) while changing the gate symbol. In CMOS design, NAND and NOR are the natural gate forms, so designers use De Morgans theorem to convert arbitrary Boolean expressions into efficient NAND-only or NOR-only implementations. The theorem extends to any number of inputs and can be applied repeatedly to transform complex nested expressions.